The present invention relates to circuitry for driving data lines of an array formed on a substrate.
Matsueda, Y., Ashizawa, M., Aruga, S., Ohshima, H., and Morozumi, S., "Defect-Free Active-Matrix LCD with Redundant Poly-Si TFT Circuit," SID 89 Digest, Vol. XX, 1989, pp. 238-241, describe a liquid crystal display (LCD) in which an active matrix includes scanning lines and data lines formed on a substrate. As shown in FIG. 1, Y-drivers for the scan lines are formed on the same substrate, along two opposite sides of the active matrix. X-drivers for the data lines are also formed on the same substrate, along the other two sides of the active matrix. As described at page 238 in relation to FIG. 1, the X-drivers can include two shift registers, 16 video lines, and a 1280 TFT array controlled by the shift registers. Each video line can be divided into eight parallel lines to provide a data input frequency at which TFT circuits can operate. As shown in FIG. 1, each of the parallel lines is connected to a TFT of every eighth data line.
Lee, S. N., Stewart, R. G., Ipri, A., Jose, D., and Lipp, S., "FAM 13.5: A 5.times.9 Inch Polysilicon Gray-Scale Color Head Down Display Chip," 1990 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 1990, pp. 220-221 and 301, describe a display in which scanning electronics can be integrated onto a glass plate along with pixel switching transistors. Both data-line and select-line driver circuits can be fabricated on a glass substrate along with polysilicon thin-film transistors. As shown and described in relation to FIG. 2, fully-redundant data scanners are at the top of array and select scanners are on left and right. As shown and described in relation to FIG. 3, gray-scale data scanners partitioned into registers driven from a bus have 25 leads connected to the inputs of four 20-stage shift registers that are driven by four external clocks separated by 90 degrees. A chop ramp scanning technique can handle the 32 gray levels color display requirement, with each data line driven by a transmission gate controlled by the output of a 5-bit counter. As shown and described in relation to FIG. 4, a five-bit gray scale counter is associated with the data scanner circuitry. During a first line period, a 5-bit gray scale code for each pixel is loaded into the data shift registers. At the end of the line period, the data is transferred from the shift register latches to the counters. During a second line period, a master data bus is ramped by a low impedance driver from 0V to 5V, as shown in FIGS. 6a and 6b. The master data line ramp is always the same and does not contain any image information. The analog information presented to the data lines depends entirely on the contents of their counters. The counter clock increments all data line counters, and whenever each counter reaches a count of 11111, it sets the control-latch flip-flop to turn off the transmission gate. This chop ramp scanning circuit can achieve accurate, uniform 32 step digital-to-analog conversion, and integration of the scanning circuitry can reduce the number of input leads. The data line driving circuitry includes only one analog input line, referred to as a ramp line. The ramp line provides a ramp signal to a channel lead of every transfer gate TFT. For each data line's TFT, a counter is connected between the shift register and the TFTs gate to ensure that each data line receives only its signal. FIG. 8 shows timing for the circuitry in FIG. 3, showing the RAMP line as an analog signal. FIG. 9 shows a chop ramp technique for gray scale conversion.
Lewis, EP-A 0 540 163, describes switched capacitor analog circuits constructed from polysilicon (poly-Si) TFTs and thin film capacitors (TFCs). The circuits can be fabricated on large area substrates and integrated with, for example, flat panel displays, pagewidth optical scan arrays, or pagewidth printheads. The analog switched capacitor circuits can be used to form data drivers, including sampling amplifiers and digital-to-analog converters (DACs) for AMLCDs. As shown and described in relation to FIGS. 5-9, switched capacitor amplifiers settle with cycle times well below 60 .mu.s, the approximate line time available for a conventional TV resolution AMLCD; in addition, the amplifiers respond with good linearity and without clipping. As shown and described in relation to FIGS. 10-13B, all thin-film charge redistribution DACs can be constructed for AMLCD data driving or other applications. As shown and described in relation to FIGS. 14A and 14B, an array of video sampling amplifiers with polysilicon TFT components can be used to drive the data lines of an AMLCD. As shown and described in relation to FIGS. 15A and 15B, a display driver architecture can use DACs implemented entirely in TFTs and TFCs, with a multiplexer at the output of each DAC, allowing each DAC to drive several lines by switching the DAC output between the data lines.